KAIST Researchers Develop New Method to Define Quantum Limits of Transistor Miniaturization

• June 17, 2026

Researchers at the Korea Advanced Institute of Science and Technology (KAIST) have formulated a new methodology to precisely determine the quantum boundary for reducing transistor sizes. This advancement sheds light on the fundamental physical constraints affecting transistor miniaturization, driven primarily by quantum tunneling phenomena.

As semiconductor manufacturers continue to pursue ever smaller transistor structures to enhance computing performance and energy efficiency, they encounter a critical challenge. Beyond a certain scaling threshold, quantum tunneling causes uncontrollable increases in leakage current, deteriorating device reliability and power consumption.

Quantifying Quantum Constraints for Transistor Scaling

The KAIST team’s approach provides a quantitative framework for understanding when and how quantum effects start to dominate transistor behavior. By methodically calculating the point at which electron tunneling leads to unacceptable leakage currents, this method offers insight into the physical lower bound of transistor miniaturization.

In addition to defining this quantum limit, the researchers’ methodology enables chip manufacturers to evaluate potential countermeasures for suppressing tunneling-related leakage. This could allow advancements in transistor design and materials science aimed at pushing device scaling closer to its theoretical minimum without succumbing to the inefficiencies caused by quantum effects.

Traditionally, transistor size reductions have been driven by empirical methods and incremental improvements guided by trial and error. The KAIST framework shifts this paradigm by providing a conscious, physics-based basis for determining the feasibility of further scaling and for guiding innovation in nanoscale transistor architectures.

This development comes at a time when the semiconductor industry faces growing technical challenges in continuing Moore’s Law, the long-standing trend of doubling transistor density approximately every two years. With the increasing prominence of quantum mechanical effects at nanoscale dimensions, tools that clarify the fundamental boundaries of transistor scaling are becoming invaluable.

While specific implementation details and practical adaptations of the KAIST methodology to commercial chip fabrication require further development, this research represents a crucial step toward understanding and potentially overcoming the limits imposed by quantum tunneling in nanoelectronics.

Ultimately, this work equips semiconductor researchers and manufacturers with a clearer roadmap for transistor innovation, balancing size reduction objectives against the unavoidable quantum behaviors that emerge as devices approach atomic scales.

Scientists at KAIST introduced a method to quantify the quantum limits of transistor scaling, addressing current leakage challenges.